1. Field of the Invention
The present invention generally relates to electrical circuits and their fabrication. More particularly, this invention relates to a process for forming a microelectronic assembly with photodefined integral capacitors having self-aligned dielectric and electrodes.
2. Description of the Prior Art
Integral capacitors for hybrid microelectronic circuits are typically fabricated by forming and patterning a conductive region on a substrate to define a bottom electrode, depositing a thin (20 to 50-micrometer) layer of dielectric material on the substrate and over the bottom electrode to form a capacitor dielectric, and then plating or otherwise metallizing the dielectric to form a second conductive region that is etched or otherwise patterned to define a top electrode. As is well known, the capacitance of an integral capacitor is given by
C=KEA/t
where K is the dielectric constant or relative permittivity of the dielectric material, E is the permittivity of free space (a physical constant), A is the area of the capacitor (that is, the area by which the top electrode overlaps the bottom electrode), and t is the thickness of the dielectric.
From the above equation, a high dielectric constant and a small dielectric thickness are desirable to achieve a high capacitance per unit area. However, each of these approaches presents difficulties. It is well known that the dielectric constant of polymer materials (typically less than four) can be increased by filling the polymer with ceramic particles, fibers or platelets, e.g., barium titanate or lead titanate-doped lead magnesium niobate. Employing such a high permittivity dielectric, however, requires a departure from typical multilayer circuit constructions. Though often done (and as represented in FIGS. 1 and 2 by dielectric layers identified by reference numbers 112 and 118), it is generally undesirable to have the dielectric material that forms the capacitor dielectric present on other regions of a circuit board because the dielectric ceramic filler increases parasitic capacitance between other circuit features. A second difficulty presented by ceramic-filled resins, especially at high ceramic volume fills (e.g., about 30 to 60%) is that they cannot be electroplated as easily as pure resins for the formation of capacitor top electrodes.
Additional difficulties arise when the dielectric thickness is reduced. The thickness of a dielectric layer over features (e.g., capacitor electrodes) on a circuit board can be difficult to control because dielectric thickness is strongly influenced by the dimensions of the patterned features over which the dielectric is deposited. As can be seen from FIG. 1, a dielectric layer 112 tends to planarize well over a narrow feature (e.g., electrode) 114, but poorly over large features 116, with the result that dielectric thickness can vary between adjacent capacitors and possibly within a single capacitor electrode. This causes two problems. First, there is a danger of metal-to-metal shorts through the very thin dielectric covering the narrow feature 114. Second, desirable tolerances for capacitor values, e.g., less than 10%, are difficult to achieve for integral capacitors on a circuit board that requires a wide range of capacitor values and hence electrode sizes.
Another difficulty in achieving acceptable capacitor tolerances arises as a result of the difficulty of aligning the capacitor electrodes relative to each other. As illustrated in FIG. 2, even if a uniform thickness for a capacitor dielectric 118 can be achieved, there is a tendency for electrode misalignment, as represented by the bottom electrode 120 and top electrode 122. Such misalignment alters the capacitance through reduction of the capacitor area (xe2x80x9cAxe2x80x9d in the capacitance equation above). As a partial solution, the prior art has resorted to making one of the electrodes (e.g., the bottom electrode 124 of FIG. 2) larger than the other (e.g., the top electrode 126 of FIG. 2) to prevent electrode misalignment that would reduce the effective capacitor value.
Accordingly, it would be desirable if a method were available for forming integral capacitors that produced capacitor dielectrics of uniform thickness and well-aligned electrodes in order to promote high capacitance density, capacitor tolerances of less than 10%, and reduced risk of interlayer shorts.
The present invention provides a method for manufacturing a microelectronic assembly to have aligned conductive and dielectric regions with desirable processing and dimensional characteristics. The invention is particularly useful for producing integral capacitors, with the desired processing and dimensional characteristics achieved with the invention yielding predictable electrical characteristics for the capacitors.
The method of this invention generally entails providing a substrate with a first conductive layer, forming a dielectric layer on the first conductive layer, and then forming a second conductive layer on the dielectric layer. A first region of the second conductive layer is then removed to expose a first region of the dielectric layer, which in turn is removed to expose a first region of the first conductive layer that is also removed. From this process, a second region of the first conductive layer remains, which is covered by a second region of the dielectric layer, which in turn is covered by a second region of the second conductive layer. According to this invention, the first regions of the conductive and dielectric layers are each removed by using the overlying layer or layers as a mask, so that the remaining second regions of these layers are coextensive, i.e., their perimeters are accurately aligned with each other. The resulting structure can define a capacitor, in which the second regions of the first and second conductive layers define capacitor electrodes and the second region of the dielectric layer defines a capacitor dielectric between the capacitor electrodes.
According to this invention, the first regions of the conductive and dielectric layers are preferably removed by etching the conductive layers and photodefining the dielectric layer. For the latter, the dielectric layer is preferably formed of a positive-acting photosensitive dielectric material, and the first region of the dielectric layer is removed by using the second region of the second conductive layer as a photomask. Also preferred is that the second conductive layer is a metal foil that can be laminated directly to the dielectric layer, as opposed to being plated or otherwise deposited.
In view of the above, this invention makes possible integral capacitors with self-aligned dielectric and electrodes, so that multiple capacitors can be formed on a microelectronic assembly, each being patterned to accurately obtain desired capacitances by the ability to form dielectrics of uniform thickness between aligned electrodes. In particular, alignment between conductive and dielectric layers is achieved by defining each layer using its overlying layer (or layers) as a mask, while uniform thickness of the dielectric is achieved as a result of the dielectric being deposited on the first conductive layer while still unpatterned. The invention also eliminates the need to roughen and plate the dielectric for the top electrode, so that the ceramic content of the dielectric is not an issue in terms of adhesion between the top electrode and the dielectric. The invention further enables the use of high-k ceramics in the dielectric without increasing parasitic capacitance because the dielectric containing the high-k ceramic can be precisely limited to the capacitor. As a result, interconnect lines can be formed closely adjacent to the capacitor electrodes.
Other objects and advantages of this invention will be better appreciated from the following detailed description.